As shown in FIG. 1, it is a computer system architecture. In a modern computer system, CPU 20, memory 22, and graphic chip 24 work very closely and they need to have faster data access to each other. As a result, requests and responses issued from the three devices are all controlled and managed by the north bridge chip 26. The north bridge chip 26 is tied to the south bridge chip 28, which routes traffic from the different I/O devices on the system, such as hard disk drive 30, optical disk drive 32, and ethernet port 34. The traffic from these devices is routed through the south bridge chip 28 to the north bridge chip 26 and then onto the CPU and/or memory 22.
In 2002, a new PCI express bus specification was finished and then a PCI express bus 40 communicated between the graphic chip 24 and the north bridge chip 26 was implemented in the computer system. Generally speaking, a connection between a graphic chip 24 and the north bridge chip 26 on a PCI express bus 40 is called a link. Each link is composed of one or more lanes, and each lane is capable of transmitting one byte at a time in both directions. That means each lane is itself composed of one pair of signals: send and receive. In order to transmit PCI express packets, which are composed of multiple bytes, one device using a one-lane link on the transmitting end must break down each packet into a series of bytes, and then transmit the bytes in rapid succession. The device on the receiving end has to collect all of the bytes and then reassemble them into the original packet.
One of PCI express bus 40 features is the ability to aggregate multiple individual lanes together to form a signal link. In other words, two lanes could be coupled together to form a single link capable of transmitting two bytes at a time, this doubling the link bandwidth. Also, four lanes, or eight lanes could be combined to form a single link. A link composes of a single lane is called an x1 link; a link composed of two lanes is called x2 link; a link composed of four lanes is called x4 link, etc. PCI express bus 40 supports x1, x2, x4, x8, x12, x16, and x32 link widths. Furthermore, PCI express bus supports two different link speeds. One is called PCI express generation 1 (Gen 1) having a clock data rate of 2.5 GHz, and the other is called PCI express generation 2 (Gen 2) having a clock data rate of 5 GHz.
As depicted in FIG. 2, it is a conventional method for devices connecting to a PCI express bus to negotiate a link width/speed. Conventionally, link width/speed is reset when link is down or initial power up. The first state is called link down state or initial power up state 50, which is set at the time of powering up the computer system. Then, the state changes to set maximum link width/speed state 52, which is activated by two devices connected by the PCI express bus. In the state 52, two devices individually set the maximum link widths/speeds they support for transmitting and receiving data through the bus. Then, the state changes to negotiate maximum allowed link width/speed state 54. In state 54, two devices negotiate an allowed maximum link width/speed according to the physical layer electrical characteristic, and channel features of both devices. For example, in state 52, the respective maximum link bandwidths of graphic chip and north bridge chip are x32/Gen1 and x16/Gen2. After negotiation process of state 54, the maximum allowed link width/speed of PCI express bus is x16/Gen1. After the maximum allowed link width/speed is determined, there is generally also device initiation/configuration state 56 for devices to be useful in a real application. After state 56, it goes to link normal operation state 58, which means the maximum allowed link bandwidth is the final operation bandwidth for the two devices to communicate normally with each other.
According to FIG. 2, to change link width/speed, it should disable the link or power down the computer system for the state to go from link normal operation state 58, through link down/initial power up state 50, set maximum link width/speed state 52 negotiate maximum allowed width/speed state 54, then to device initiation/configuration state 56. Since the execution of link down/initial power up state 50 and device initial/configuration state 56 to change link width/speed is complicated and time consuming. In real practice, the maximum allowed speed/width is always set for all applications. In other words, link bandwidth never changes, and there is no bandwidth management needed in the prior art. In other cases, the final operation bandwidth is always the maximum allowed link width/speed even if the link bandwidth is to be changed. Moreover, for bandwidth eager applications, e.g. 3D game software, the preset bandwidth may be too small; and for applications with few packets traffic, e.g. document software, the preset bandwidth is often too luxury for them, which in most cases means power waste.